FSM in VHDL - Fabio Panozzo

FSM in VHDL Macchina a sta@ fini@ – Moore IN NEXT STATE LOGIC NEXT STATE CURRENT STATE RST OUTPUT LOGIC CLK Esempio: Macchina di Moore a due sta/ 1 0 S0/0 RST 0 S1/1 1 OUT Esempio: Macchina di Moore (3 process) entity moore is
port( clk,rst,input: in bit;
output:out bit);
end moore;
architecture ex1 of moore is
type state_type is (S0,S1);
signal current_state, next_state: state_type;
begin
ff: process (clk,rst)
begin
if rst = ‘1’
then
state <= S0;
elsif (clk'event and clk = '1') then
current_state <= next_state;
end if;
end process ff;
st: process (current_state)
begin
case current_state is
when S0 =>
if input=‘0’ then next_state <= S0;
else next_state <= S1;
end if;
Esempio: Macchina di Moore (3 process) when S1 =>
if input=‘0’ then next_state <= S1;
else next_state <= S0;
end if;
end case;
end process st;
out_p: process (current_state)
begin
case current_state is
when S0 => output <= ‘0’;
when S1 => output <= ‘1’;
end case;
end process out_p;
end ex1;
Esempio: Macchina di Moore (2 process) entity moore is
port( clk, rst, input: in bit;
output: out bit);
end moore;
architecture ex2 of moore is
type state_type is (S0,S1);
signal current_state, next_state: state_type;
begin
ff: process (clk,rst)
begin
if rst = ‘1’
then
state <= S0;
elsif (clk'event and clk = '1') then
current_state <= next_state;
end if;
end process ff;
st: process (current_state, input)
begin
case current_state is
when S0 =>
output <= ‘0’;
if input=‘0’ then next_state <= S0;
else next_state <= S1;
end if;
Esempio: Macchina di Moore (2 process) when S1 =>
output <= ‘1’;
if input=‘0’ then next_state <= S1;
else next_state <= S0;
end if;
end case;
end process st;
end ex2;
Esempio: FSM_1 – Moore C_IN [0÷1] FSM_1 RST ST2
01,-0
11
Y_OUT [0÷1] 01
111
10,-1
0-
01,-0
RST
CLK ST1
00
ST3
11
ST4
10
00
00 01 11 10 Y_OUT ST1 ST2 ST2 ST1 ST2 00 ST2 ST3 ST3 ST1 ST3 11 ST3 ST3 ST4 ST4 ST4 01 ST4 ST3 ST3 ST2 ST2 10 Esempio: Codice sorgente di FSM_1 – Moore entity FSM_1 is
port ( RST, CLK : in
bit;
C_IN : in bit_vector (0 to 1);
Y_OUT : out bit_vector (0 to 1));
end FSM_1;
architecture MOORE of FSM_1 is
type STATE_TYPE is ( ST1, ST2, ST3, ST4);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
--------------------------------- Processo sequenziale
-------------------------------SEQ: process (CLK, RST)
begin
if RST = '1' then
CURRENT_STATE
<= ST1;
elsif (CLK'event and CLK = '1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process SEQ;
Esempio: Codice sorgente di FSM_1 – Moore ------------------------------------------------------------- Processo Combinatorio per Next State Logic
-----------------------------------------------------------COMB: process (current_state,C_IN)
begin
case CURRENT_STATE is
when ST1 =>
if (C_IN="00" or C_IN="01" or C_IN="10") then
NEXT_STATE <= ST2;
else
NEXT_STATE <= ST1;
end if;
when ST2 =>
if (C_IN="00" or C_IN="01" or C_IN="10") then
NEXT_STATE <= ST3;
else
NEXT_STATE <= ST1;
end if;
when ST3 =>
if (C_IN="01" or C_IN="10" or C_IN="11") then
NEXT_STATE <= ST4;
else
NEXT_STATE <= ST3;
end if;
Esempio: Codice sorgente di FSM_1 – Moore when ST4 =>
if ( C_IN="00" or C_IN="01") then
NEXT_STATE <= ST3;
else
NEXT_STATE <= ST2;
end if;
end case;
end process COMB;
------------------------------------------ Processo Combinatorio per Output Logic
----------------------------------------OUT_LOGIC: process (CURRENT_STATE)
begin
case CURRENT_STATE is
when ST1 =>
Y_OUT <= "00";
when ST2 =>
Y_OUT <= "11";
when ST3 =>
Y_OUT <= "01";
when ST4 =>
Y_OUT <= "10";
end case;
end process OUT_LOGIC;
end MOORE;
Esempio: FSM_A – Moore X 1
S1
FSM_A 1
Z 1
S2
1
1
0
S0
CLK 0
X = 0 X = 1 Z S0 S0 S2 0 S1 S0 S2 1 S2 S2 S3 1 S3 S3 S1 0 0
1
0
S3
0
0
Esempio: Codice sorgente di FSM_A – Moore entity FSM_A is
port( X, CLK: in bit;
Z: out bit);
end FSM_A;
architecture MOORE of FSM_A is
type STATE_TYPE is ( S0, S1, S2, S3);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
SEQ: process
begin
wait until(CLK'event and CLK = '1');
CURRENT_STATE <= NEXT_STATE;
end process SEQ;
COMB_OUT:process (CURRENT_STATE, X)
begin
case CURRENT_STATE is
when S0 =>
Z <= ‘0’;
if (X = ‘0’) then
NEXT_STATE <= S0;
else
NEXT_STATE <= S2;
end if;
Esempio: Codice sorgente di FSM_A – Moore when S1 =>
Z <= ‘1’;
if (X = ‘0’) then
NEXT_STATE <= S0;
else
NEXT_STATE <= S2;
end if;
when S2 =>
Z <= ‘1’;
if (X = ‘0’) then
NEXT_STATE <= S2;
else
NEXT_STATE <= S3;
end if;
when S3 =>
Z <= ‘0’;
if (X = ‘0’) then
NEXT_STATE <= S3;
else
NEXT_STATE <= S1;
end if;
end case;
end process COMB_OUT;
end MOORE;
Macchina a sta@ fini@ – Mealy NEXT STATE LOGIC and OUTPUT LOGIC IN OUT NEXT_STATE CURRENT_STATE RST CLK Esempio: FSM_B – Mealy 1/0
X STC
STA
0/1
1/1
Z 0/0
0/0
CLK X = 0 X = 1 STA STB / 0 STC / 0 STB STB / 0 STD / 0 STC STC / 1 STD / 0 STD STD / 0 STA / 1 STB
1/0
1/0
STD
0/0
Esempio: Codice sorgente di FSM_B – Mealy entity FSM_B is
port ( X, CLK: in bit;
Z: out bit);
end FSM_B;
architecture MEALY of FSM_B is
type STATE_TYPE is ( STA, STB, STC, STD);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
SEQ: process
begin
wait until(CLK'event and CLK = '1');
CURRENT_STATE <= NEXT_STATE;
end process SEQ;
COMB_OUT:process (CURRENT_STATE, X)
begin
case CURRENT_STATE is
when STA =>
if (X = ‘0’) then
Z <= ‘0’;
NEXT_STATE <= STB;
else
Z <= ‘0’;
NEXT_STATE <= STC;
end if;
Esempio: Codice sorgente di FSM_B – Mealy when STB =>
if (X = ‘0’) then
Z <= ‘0’;
NEXT_STATE <= STB;
else
Z <= ‘0’;
NEXT_STATE <= STD;
end if;
when STC =>
if (X = ‘0’) then
Z <= ‘1’;
NEXT_STATE <= STC;
else
Z <= ‘0’;
NEXT_STATE <= STD;
end if;
when STD =>
if (X = ‘0’) then
Z <= ‘0’;
NEXT_STATE <= STD;
else
Z <= ‘1’;
NEXT_STATE <= STA;
end if;
end case;
end process COMB_OUT;
end MEALY;