+ B

1
Moduli aritmetici
q sommatori
q moltiplicatori
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
2
Sommatori
Somme e sottrazioni fra operandi a N bit
A={A0, A1,… A(N-1)} e B= {B0, B1,… B(N-1)}
con rappresentazione in complemento a 2
q A+B = Sum
Sumi= Ai + Bi + Cini
Couti = Cin(i+1) = AiBi+Cini(Ai + Bi)
q A-B = A+(B +1)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
1
3
Sumi= Ai + Bi + Cini = Pi + Cini
Full-Adder
Couti=AiBi+Cini(Ai + Bi) = Gi + Cini Pi
AB
A+B
A⊕ B
A B
0
0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
G
P
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
D
a.a. 2008-2009
Complementary Static CMOS Full Adder
4
VDD
VDD
A
Ci
A
B
B
A
B
B
Ci
A
X
Ci
Ci
VDD
y
A
S
Ci
A
B
B
VDD
A
B
Co
28 Transistors
Co=AB + Ci(A+B)
Cin,eq (ci)=3Cnot
Ci
A
B
S=ABCi + Co(A+B+Ci)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
2
5
Serial adder
registri a
scorrimento
FA
AN-1
A2
A1
BN-1
B2
B1 Bo
Ao
A
S
B
Cout
SN-1
S1 So
Cin
Reset
Q
D
tadder = N Tck
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
6
The Ripple-Carry Adder
A0
Ci,0
B0
FA
S0
A1
Co,0
(= Ci,1)
B1
FA
A2
Co,1
S1
B2
FA
a.a. 2008-2009
A3
Co,2
S2
B3
FA
Co,3
S3
Worst case delay linear with the number of bits
td = O(N)
tadder = (N-1)tcarry + tS
Goal: Make the fastest possible carry path circuit
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
3
Look-Ahead - Basic Idea
A0, B0
Ci,0
A1, B 1
AN-1, BN-1
•••
P0 Ci,1
S0
Cin ,1 = Co , 0 = g 0 + p0Co
7
P1
Ci, N-1
S1
PN-1
SN-1
•••
Cin , 2 = Co ,1 = g1 + p1 ( g 0 + p0C0 ) = g1 + p1 g 0 + p1 p0C0
Cin , 3 = Co , 2 = g 2 + p2 ( g1 + p1 ( g 0 + p0C0 )) = g 2 + p2 g1 + p2 p1 g 0 + p2 p1 p0C0
Cin , 4 = Co , 3 = g 3 + p3 ( g 2 + p2 ( g1 + p1 ( g 0 + p0C0 ))) =
= g 3 + p3 g 2 + p3 p2 g1 + p3 p2 p1 g 0 + p3 p2 p1 p0C0
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
Carry-Bypass Adder (or Carry-Skip)
Ci,0
go
FA
p1
C o,0
p0 g o
Ci,0
FA
FA
p1
C o,0
g1
g
FA
p2
C o,1
FA
p2
1
Co,1
g
p3
2
Co,2
g2
FA
FA
p3
C o,2
g3
g3
FA
Co,3
BP=p op 1 p 2 p 3
Multiplexer
p0
8
Co,3
Idea: If (p0 and p1 and p2 and p3 = 1)
then g0=g1=g2=g3=0 and Co,3 = Ci,0
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
4
9
Carry-Bypass Adder
Bit 0–3
Bit 4–7
g,p
tg,p
g,p
Bit 8–11
tmux
Bit 12–15
g,p
Carry
propagation
Carry
propagation
Carry
propagation
exor
exor
exor
g,p
Carry
propagation
exor
texor
M bits
tadder = tg,p + Mtcarry + (N/M-1)tmux + (M-1)tcarry + texor
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
10
Carry Select Adder
Bit 0–3
Bit 4–7
g,p
g,p
Bit 8–11
Bit 12–15
g,p
g,p
0
0-Carry
0
0-Carry
0
0-Carry
0
0-Carry
1
1-Carry
1
1-Carry
1
1-Carry
1
1-Carry
Ci,0
Multiplexer
Co,3
Multiplexer
Co,7
Multiplexer
Co,11
Multiplexer
Sum Generation
Sum Generation
Sum Generation
Sum Generation
S0–3
S4–7
S8–11
S12–15
Co,15
M bit
Tadder=tg,p + M tcarry + N/M tmux + texor
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
5
11
from Altera Corporation Stratix Architecture
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
12
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd,
from Altera Corporation
Stratix Architecture
2003 Prentice Hall/Pearson a.a. 2008-2009
6
13
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd,
from Altera Corporation
Stratix Architecture
2003 Prentice Hall/Pearson a.a. 2008-2009
14
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd,
from Altera Corporation
Stratix Architecture
2003 Prentice Hall/Pearson a.a. 2008-2009
7
15
“O” Operator
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
16
Properties of the “O” operator
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
8
17
Group Generate and Propagate
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
18
Group Generate and Propagate
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
9
19
Group Generate and Propagate
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
20
Applicazione dell’operatore O
((g7,p7)o(g6,p6))o((g5,p5)o(g4,p4))o((g3,p3)o(g2,p2))o((g1,p1)o(g0,p0))
(G7:6,P7:6) o (G5:4,P5:4) o
(G7:4,P7:4)
(G3:2,P3:2) o (G1:0,P1:0)
o
(G3:0,P3:0)
G7:0= Cout,7
Numero di livelli = log2N
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
10
Logarithmic Look-Ahead Adder
21
Tadder=tg,p + (log2N) to+ texor
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
Logarithmic Look-Ahead Adder
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
22
a.a. 2008-2009
11
23
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
24
The Binary Multiplication
M −1
X = ∑ xi 2
1 0 1 0 1 0
i
1 0 1 1
i =0
Y = ∑ yj 2j
∑z
n =0
n
0 0 0 0 0 0
1 0 1 0 1 0
2
Multiplier
X
1 0 1 0 1 0
j =0
Z=
Y
1 0 1 0 1 0
N −1
( N + M ) −1
Multiplicand
Partial products
(M)
n
0
1 1 1 0 0 1 1 1 0
Result
Z
(N+M)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
12
25
Serial Multiplier (N=M)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
Serial Multiplier es: M=N=4
a.a. 2008-2009
26
x3 x2 x1 x0
y3 y2 y1 y0
Y
X
Y and x0
Y and x1
Y and x2
Y and x3
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
13
27
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
28
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
14
29
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
30
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
15
The Array Parallel Multiplier
31
Y and x0 = 1010
Y and x1 = 1010
Y and x2 = 0000
Y and x3 = 1010
Es: 1010 *
1011
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
The Array Parallel Multiplier
a.a. 2008-2009
32
Y and x0 = 1010
Y and x1 = 1010
Y and x2 = 0000
Y and x3 = 1010
Es: 1010 *
1011
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
16
The NxN Array Multiplier
N
— Critical Path
N-1
FA
HA
FA
FA
FA
FA
HA
33
HA
Critical Path 1
Critical Path 2
FA
FA
FA
Critical Path 1 & 2
HA
Tmul= tand+ (N-1)tcarry + (N-1)tsum + (N-2)tcarry
Tmul= tand+ (N-2)tcarry + (N-1)tsum + (N-1)tcarry
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
y7 y6 y5 y4 y3 y2 y1 y0
34
x7 x6 x5 x4 x3 x2 x1 x0
y6 x0
y5 x0
y4 x0 y3 x0
y2 x0
y1 x0
y1 x1
y0 x2
y0 x1
z2
z1
y7 x1 y6 x1 y5 x1
y6 x2 y5 x2 y4 x2
y5 x3 y4 x3 y3 x3
y4 x4 y3 x4 y2 x4
y4 x1 y3 x1 y2 x1
y3 x2 y2 x2 y1 x2
y2 x3 y1 x3 y0 x3
y1 x4 y0 x4
y7 x4
y7 x3
y6 x4
y7 x2
y6 x3
y5 x4
y5 x5
y4 x6
y3 x7
y4 x5
y3 x6
y2 x7
y3 x5 y2 x5
y2 x6 y1 x6
y1 x7 y0 x7
y1 x5
y0 x6
y7 x7
y7 x5 y6 x5
y6 x6 y5 x6
y5 x7 y4 x7
y0 x5
y7 x6
y6 x7
z15 z14
z13
z12 z11
z10
z9
z8 z7
z6
z5
z4 z3
y0 x0
partial products
y7 x0
z0
Proprietà associativa: z2 = x2yO + x1y1 + xO y2 + Cin,2 =
della somma aritmetica (xoy2 + x1y1+Cin,2) + x2y0= Array Parrallel Multiplier
(x2y0 + x1y1)+x0y2+Cin,2
Array Carry-save Multiplier
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
17
Array-based
Carry-Save
Multiplier
35
Tmul= tand +
(N-1)max{tcarry,tsum} +
+ tadder(N-1 bit)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
4-Bit Carry-Save
Multiplier
ottimizzazione
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
36
a.a. 2008-2009
18
Transmission Gate Full Adder (Tsum=Tcarry)
37
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
38
Tree Based Multiplier: Carry-save 4:2
In1 In2 In3 In4
FA
Cout
Cin
FA
Carry
Sum
n = In1 + In2 + In3 + In4
* una e una sola delle due uscite
Cout o Carry assume il valore 1
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
19
39
y7 y6 y5 y4 y3 y2 y1 y0
x7 x6 x5 x4 x3 x2 x1 x0
y 7 x7
Z15 z14
y7 x2
y 6 x3
y 6 x0
y 5 x1
y 5 x0
y 4 x1
y 4 x0 y 3 x0
y3 x1 y 2 x1
y 2 x0
y1 x1
y 6 x2 y5 x 2
y 5 x 3 y 4 x3
y 4 x2
y 3 x3
y 3 x2
y 2 x3
y 2 x2 y1 x2
y1 x3 y 0 x3
y 0 x2
y 7 x6
y 7 x4
y 7 x5 y 6 x5
y 6 x6 y 5 x6
y 6 x4
y 5 x5
y 4 x6
y 5 x4
y 4 x5
y3 x6
y 4 x 4 y3 x4
y 3 x5 y 2 x5
y2 x6 y1 x6
y 6 x7
y 5 x7 y 4 x7
y 3 x7
y 2 x7
y1 x7 y0 x7
z13
z12 z11
z10
z9
z8 z7
y 2 x4
y1 x5
y 0 x6
z6
y1 x4
y 0 x5
y1 x 0
y 0 x1
y 0 x0
z1
z0
partial products
y 7 x3
y 7 x0
y 7 x1 y 6 x1
y0 x4
z5
z4 z3
z2
es: all’ingresso di CSA4:2 di peso 3
x0y3 , x1y2 , x2 y1 , x3 y0 e Cin generato dal CSA4:2 con
gli ingressi di peso immediatamente inferiore
Tree based Carry-save Multiplier
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
40
CSA 4:2 Adder
tCSA4:2 = 2 tFA, tFA = max {tcarry, tsum}
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
20
41
y 7 x0
y 6 x0
y5 x0
y 4 x0 y 3 x0
y 2 x0
y1 x 0
y 7 x1 y 6 x1
y5 x1
y 4 x1
y 3 x1 y 2 x1
y1 x1
y 0 x1
y7 x2
y 6 x2 y 5 x 2
y4 x2
y3 x2
y 2 x 2 y1 x 2
y 0 x2
y 6 x3
y 5 x 3 y 4 x3
y 3 x3
y 2 x3
y1 x 3 y 0 x 3
CSA 4:2 1o livello
y 7 x3
CSA 4:2 1o livello
y7 x7
y5 x4
y4 x5
y 4 x4 y3 x4
y3 x5 y2 x5
y2 x4
y1 x5
y4 x6
y3 x6
y2 x6 y1 x6
y0 x6
y3 x7
y 2 x7
y1 x7 y0 x7
y 7 x4
y7 x5 y6 x5
y6 x4
y5 x5
y7 x6
y6 x6 y5 x6
y6 x7
y5 x7 y4 x7
CSA 4:2 2o livello
y1 x4
y0 x5
y 0 x0
y 0 x4
sl10 sl9 sl8 sl7 sl6 sl5 sl4 sl3 sl2 sl1 sl0
cl11 cl10 cl9 cl8 cl7 cl6 cl5 cl4 cl3 cl2 cl1
sh14sh13sh12sh11sh10sh9sh8sh7sh6sh5sh4
ch15ch14ch13ch12ch11ch10ch9ch8 ch7ch6ch5
r15 r14 r13 r12
r11 r10 r9 r8
r7 r6 r5
r4 r3 r2 r1 r0
c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
8-bit Binary Tree
42
8 bit
11 bit (sh,ch)
11 bit (sl, cl)
16 bit (r,c)
sommatore a 16 bit
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
21
43
Operandi a 16 bit (N=16)
T = tand + (log2N/2)tcsa4:2 + tadder(2N bit)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
44
(1)
(+)
from Altera
Corporation
Stratix Architecture
(+)
(3)
(+)
(4)
(1)
(2)
(3)
(4)
B17:0 x A17:0
B35:18 x A17:0
B35:18 x A35:18
B17:0 x A35:18
(2)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
22
45
Serial Multiplier
q
Tmul= N Tck
A = Aadder(N)
Tck = tadder (Nbit) + tand + tshift
Parallel Multiplier
q
Array–based Carry Save
§
T = (N-1)tFA + tadder(N-1 bit) + tand
A = (N-1)(N-1)AFA + Aadder(N-1)
Tree-based (binary tree)
§
T = 2 log2(N/2)tFA + tadder(2N bit) + tand
A = N(N-2)AFA+ Aadder(2N)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
Binary tree multiplier: Pipeline
a.a. 2008-2009
46
Ck
Ck
8
CSA 4:2
CSA 4:2
11
CSA 4:2
16
Ck
NxN, N=8
Sommatore a 16 bit
Ck
Tck = max [(log2N/2)tcsa4:2, log2(2N)to] = max [2(log2N/2)tFA, log2(2N)to]
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson
a.a. 2008-2009
23