Architetture di bus per System-On-Chip System-on

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Architetture di bus per
System-On-Chip
Massimo Bocchi
Corso di Architettura dei Sistemi Integrati
A.A. 2002/2003
System-on-chip motivations

400
Transistors
(Millions)/Chip
300
200

Technology
(nm)
100
0
Growing transistor count
on a single chip
Implementation of a
greater number of
functionalities
1997 1999 2001 2003 2005 2007 2009

Logic
SRAM
Flash
E-DRAM
CMOS RF
FPGA
FRAM
MEMS
Chemical sensors
Electro-optical
Electro-biological
98
00
Massimo Bocchi, 07/02/2003
02
04
06
08
New technologies
integrated on the same
chip
10
ARCES - University of Bologna
1
Intellectual property reuse

Design complexity
– High number of components
– Integration of different
technologies

Critical TimeTime-toto-market
Low cost design
IntellectualIntellectual-property (IP)
Reuse, among other
design technologies, has
generated the higher
productivity increase.
“Semiconductor intellectualintellectual-property designers strive to ensure
their IP can be used by the widest possible range of applications
applications to
ensure maximum return on their engineering investment.”
Ed Smith (Sonics Inc.), 2002
IP-Reuse evolution
Small blocks reuse
(registers, multiplexer, adders,
multipliers, shifters, …)
Large blocks reuse
(embedded processors, memory controllers,
I/O interfaces, DMA controllers, …)
System reuse
(suitable for multiprocessor systems development,
networksnetworks-onon-chip, …)
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IP vs. IC
IPIP-based design
ICIC-based design
The basic components are
described using a hardware
description language (HDL)
The basic components consist of
several integrated circuits
The components are collected
into IPIP-libraries
The components are collected
into ICIC-libraries
The whole system is
implemented on a single chip
All the components are placed on
a board
Bus architectures
A bus architecture specification provides:
interfaces for the components placed on
the bus
protocols for on-chip communication and
signals transmission
architectural description of the hardware
connections between the peripherals
included into the system
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Bus architectures
How bus architectures can improve SoC design:
Standard interfaces support IP-Reuse
methodology allowing the creation of Plug and
Play cores
SoC designs are more reliable if based on a
standard bus architecture
Test methodologies can be improved and
supported by standard test interfaces
Cost reduction for verification tasks
Bus architectures comparison
WISHBONE

– Power consumption
reduction
– Performance increase
AMBA
CoreConnect
System and
peripheral bus

De facto standard
for onon-chip bus
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AMBA specification

AMBA is an open standard developed by ARM Ltd.
Ltd.
(www.arm.com)
A typical AMBAAMBA-based SoC consists of a high
performance system bus (AHB) and peripheral bus (APB)
A standard test methodology is included in the AMBA
specification
The full AHB specification is contained in the AMBA 2.0
documentation
AHBAHB-Lite is a subset to the full AHB specification
MultiMulti-layer AHB is an extension to the AHB protocol,
protocol,
providing parallel communication paths between masters
and slaves
A typical AMBA-based SoC
Test
Interface
Controller
DMA bus
master
High
performance
processor
AHB bus
Arbiter
High
Bandwidth
On-chip
Memory
interface
High
Bandwidth
On-chip
Memory
interface
Massimo Bocchi
Parallel
Port
B
R
I
D
G
E
Display
controllers
APB bus
Timer
UART
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AMBA AHB main features
Pipelined
operation
Multiple bus masters
Burst transfers
Split transactions
Non-tristate implementation
Wide data bus configurations (up to 128
bits)
AMBA APB main features
Low
power consumption
Simple interface
Latched address and control
Suitable for many peripherals
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AHB single transfer
HCLK
HADDR &
Control
A
HREADY
Data (A)
HRDATA
Data (A)
HWDATA
The addressed slave can insert one or more wait cycles if the
data phase has to be delayed
AHB masters states
no transfers
or busy bus
new burst or single transfer
IDLE
no transfers
no
transfers
BUSY
ready for transfer
not ready for transfer
single
transfer
NONSEQ
single
transfer
burst
transfer
SEQ
burst
transfer
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AHB slaves responses

OKAY: the transfer has been completed
successfully
ERROR: there was an error during the transfer;
the master should reinitiate the transfer
RETRY: the slave has not yet completed the
transfer; the master should retry a new transfer
SPLIT: the slave cannot complete the transfer
immediately; another higher-priority master can
get access to the bus and the current transfer
will be completed later
Burst transfers
Type
Description
SINGLE
Single transfer
INCR
Incrementing burst of unspecified length
WRAP4
4-beat wrapping burst
INCR4
4-beat incrementing burst
WRAP8
INCR8
WRAP16
INCR16
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AHB bus interconnection
APB transfers
The
BRIDGE operates signal conversions
from the AHB protocol to the APB one
APB features a very simple communication
protocol
APB slaves cannot insert any wait cycle;
the duration of transfers is fixed
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APB state diagram
no
transfer
transfer
IDLE
SETUP
no
transfer
transfer
ENABLE
AHB-Lite specification

Only one bus master is supported
The resulting system can be:
– a simple system containing only one bus master
– a MultiMulti-layer AHB system containing only one bus
master per layer

AHB-Lite simplifies the full AHB specification:
– no arbitration is required, since the Request/Grant
Request/Grant
protocol is not used
– the AHB slaves don’t
don’t have to support Split/Retry
Split/Retry
responses
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Multi-layer AHB specification

Parallel paths connecting more than one
master/slave
Each layer can use a simplified architecture
based on the AHB-Lite protocol
Arbitration is distributed in each slave that can
be accessed by more than one master
simultaneously
An interconnect matrix is implemented using
several multiplexer to select only one master
input for each slave
Multi-layer AHB specification
Interconnect
Matrix
Slave 1
Master 1
Slave 2
Master 2
Slave 3
Master 3
Slave 4
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