Virtual memory
Transcript
Virtual memory
Computer Systems Design applied computer science urbino worldwide campus 03.04 Virtual memory 03 Memory hierarchy 03.04 Virtual memory • • • • • Virtual memory vs caching Segmentation vs paging Management policies Address translation Putting it all together alessandro bogliolo isti information science and technology institute Computer Systems Design 1/16 applied computer science urbino worldwide campus 03.04 Virtual memory Virtual memory • Uses secondary storage to extend the address space beyond physical memory • The CPU produces Virtual addresses that need to be translated into Physical addresses • Relocation: a program can run in any location in physical memory • Protection: a process can access only the memory blocks allocated to it alessandro bogliolo isti information science and technology institute 2/16 1 Computer Systems Design applied computer science urbino worldwide campus 03.04 Virtual memory Virtual memory vs caches Caching Cache Main Memory Block Cache miss Replacement mainly controlled by HW Parameter Block (page) size Hit time Miss penalty (access time) (transfer time) Miss rate Mapping Virtual Memory Main Memory Disk Segment / Page Page fault Raplecement mainly controlled by SW L1 Cache 16-128 bytes 1-3 Tclk 8-150 Tclk 6-130 Tclk 2-20 Tclk 0.1-10% 25-45 bit to 14-20 alessandro bogliolo Virtual Memory 4 - 64 Kbyte 50-150 Tclk 106-107 Tclk 8E5-8E6 Tclk 2E5-2E6 Tclk 0.00001-0.001% 32-64 bit to 25-45 isti information science and technology institute Computer Systems Design 3/16 applied computer science urbino worldwide campus 03.04 Virtual memory Segments vs pages Page Constant Block size Words per address One Segment Variable Two (segment and offset) Visibility Invisible to application programmer May be visible to application programmer Replacement Trivial (all blocks are the same size) Hard (must find contiguous, variable-size, unused space in main memory) Fragmentation Internal (unused portion of External (unused space a page) between segment) Disk traffic Efficient (adjust page size Inefficient (small segments may transfer only a few bytes) to balance access time and transfer time) alessandro bogliolo isti information science and technology institute 4/16 2 Computer Systems Design applied computer science urbino worldwide campus 03.04 Virtual memory Virtual Mem: block placement • Where can a block be placed in main memory? – Address miss involves access to secondary storage • Very long miss penalty imposes to reduce miss rate – Memory hit of non-cached addresses takes tens of clock cycles • Memory access time hides block identification time • The block placement strategy in main memory is typically fully-associative alessandro bogliolo isti information science and technology institute Computer Systems Design 5/16 applied computer science urbino worldwide campus 03.04 Virtual memory Virtual Mem: block identification • How is a block found if it is in main memory? – Both paging and segmentation rely on data structures indexed by the page or segment number alessandro bogliolo isti information science and technology institute 6/16 3 Computer Systems Design applied computer science urbino worldwide campus 03.04 Virtual memory Virtual Mem: block replacement • Which block should be replaced on a cache miss? – In order to minimize cache misses, the LRU policy is usually implemented – Replacement is managed by the Operating System – Many processors provide a used flag associated with each page (segment) to support an approximation of LRU: - the flag is periodically reset Candidates for replacement on a miss are blocks with flag 0 (i.e., unused since last reset) alessandro bogliolo isti information science and technology institute Computer Systems Design 7/16 applied computer science urbino worldwide campus 03.04 Virtual memory Virtual Mem: write strategy • What happens on a write? 1. Write through – not applicable because of the great discrepancy between access times of main memory and secondary storage devices 2. Write back – the information is written only in main memory (or, possibly, in cache). The modified block is written back to the secondary storage device when it is replaced • A dirty bit is used to mark modified blocks to be written back alessandro bogliolo isti information science and technology institute 8/16 4 Computer Systems Design applied computer science urbino worldwide campus 03.04 Virtual memory Address translation (segmentation) Virtual CPU CPU Physical MMU MMU RAM RAM ST segment table s so limit base > + error alessandro bogliolo isti information science and technology institute Computer Systems Design 9/16 applied computer science urbino worldwide campus 03.04 Virtual memory Address translation (paging) Virtual CPU CPU MMU MMU Physical RAM RAM PT page table vpn po rpn alessandro bogliolo rpn po isti information science and technology institute 10/16 5 Computer Systems Design applied computer science urbino worldwide campus 03.04 Virtual memory Address translation (paging) Virtual CPU CPU Physical MMU MMU RAM RAM PT page table vpn1 vpn2 po rpn PT2 po rpn alessandro bogliolo isti information science and technology institute Computer Systems Design 11/16 applied computer science urbino worldwide campus 03.04 Virtual memory Address translation (paged segments) virtual address s so segment table limit base C PT + A B linear address vpn1 vpn2 po page table PT2 physical address rpn po C B A rpn alessandro bogliolo isti information science and technology institute 12/16 6 Computer Systems Design applied computer science urbino worldwide campus 03.04 Virtual memory Address translation (Translation Lookaside Buffer, TLB) alessandro bogliolo isti information science and technology institute Computer Systems Design 13/16 applied computer science urbino worldwide campus 03.04 Virtual memory Cache and Virtual memory Physical cache: address translation needed to access the cache CPU CPU Virtual MMU MMU Physical Cache Cache RAM RAM Virtual cache: no address translation needed to access the cache CPU CPU Virtual MMU MMU Physical RAM RAM Cache Cache alessandro bogliolo isti information science and technology institute 14/16 7 Computer Systems Design applied computer science urbino worldwide campus 03.04 Virtual memory Cache and Virtual memory alessandro bogliolo isti information science and technology institute Computer Systems Design 15/16 applied computer science urbino worldwide campus 03.04 Virtual memory Cache and Virtual memory Alpha 21264 alessandro bogliolo isti information science and technology institute 16/16 8