STMicroelectronics chips

STMicroelectronicschips
ATLASITKItalymee7ng,14/03/2016
AAlioAndreazza,M.Ci'erio,V.Liberali,C.Meroni,F.Ragusa,E.
Zaffaroni-INFNMilano
M.Biaso=,G.Darbo,G.Gariano,A.Gaudiello,C.Gemme,P.
More=ni,L.Rossi,E.Ruscino,M.Sannino–INFNGenova
C.Sbarra,A.SidoH,F.Fabbri–INFNBologna
H.Shrimali,I.Yadav,A.Yoshi–IITMandi
Overview
•  Reminderofpassivediodeperformance
•  TestofacHvepixels
–  amplifierdesign
–  injecHoncircuitry
–  performance
•  Submissionof3×4mm2array
–  STMpostponedsubmissionHmeto22ndApril
–  Hybridiza7oninAndrea’stalktoday
–  Simula7oncoveredinFederica’stalktomorrow
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KC35A
LayoutoftheSTMtestchip(KC53A):
•  22I/OandVDD/GNDpads
•  8pixels(50x250µm2):CollecJngdiode+Amp.
•  4pixels(50x250µm2):CollecJngdiodeonly
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FirstversiondeliveredJuly2015:
•  shortsbetweenpowerlinesandground
Fixedversiondelivered29Jan.16
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Designandlayoutby:
Ø  H.ShrimaliandV.Liberali(MI)
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Passivediodes:I-V
INTERNAL DIODES SCHEMA
•  I-Vmeasurements(andC-Vaswell)needto
keepintoaccountESDprotecHondiodes:
–  0.8-1.4pAleakagecurrent@50V
on50×250μm2pixels
–  wholechipleakagecurrent,dominatedby
buriedlayerbelowI/Opads
•  “Programmed”break-downat70V.
•  STMwouldlikeustosetalsoprotecHons
betweenSUBandGND(mulHple7V
breakdownstructures)
Sensor
Buried layer
(below pads)
VDD-GND
protection
Other I/O pads
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-3-2-10
●D1
▴D2
I[pA]
Vbias[V]
-60-50-40-30-20-10
Diode pad
protections
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Passivediodes:C-V
CV MEASUREMENTS
0.20.40.60.81.01.2
•  Measuredcapacitanceparameterizedas:
C[pF]
1,4
1,2
︎D1
◆D2
▼D3
▲D4
1
0,8
–  CP:parasiHccapacitance
–  Vo:built-involtage
D1 (pF)
D2
D3
D4
0,6
0,4
0,2
Substratedatasheet:
100-150Ωcm
–  -70
-60-50-40-30-20-10
-60
-50
-40
-30
-20
-10
0
0
Vbias[V]
•  MeasurementcompaHblewith
expectaHon:k=1.8V-1pF-2
•  CorrespondingdepleHonis
22-24μmat50V
Q = eAdN A
Outputpads0.12-0.15pF
V = eN A d 2 / 2ε
C=
Q 2ε A
=
V
d
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Passivediodes:sourcetests
•  Crosscheckratewith241Amsource
•  LowrateduetosmallacHvevolume
–  photoelectricpeakat~0.1Hzratewith1mCisource
–  rateproporHonaltodepleHon(asexpected)
–  peakshapedependentondepleHon(rangeof60keVelectroninSi~33μm)
Counts/W
Counts Energy(eV) with Am source [A
E>30keV
30
E>40keV
25
20
Vbias[V]
Counts
E>50keV
15
10
5
0
Energy (eV)
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(Time 70 min)
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Ac7vepixels:powerconsump7on
Fig. 6 Output at the NWELL terminal with applying current injecting pulse of 10 nA and 10 ns.
Analog signal processing circuitry
•  CurrentabsorpHon:0.28mA(VDD=1.8V)
The particle signal, detected at the NWELL terminal of the DNWSUB is amplified using
folded
cascode single ended amplifier. The MOM capacitor (MOM) is use to block DC quantity of
•  correspondsto35μApixel
the input signal. The purely AC quantity is applied to the amplifier. The input is given to a pMOS
•  inagreementwithexpectaHonfromthedevicesimulaHon:
device
so that better noise performance can be achieved, comparing an nMOS input stage. The
amplifier
composed of DC biasing circuit [3] [4] and the gain stage [2]. The complete circuitry
–  is
9μAfortheamplifier
including
biasing is shown in Fig. 7.
–  current
25μAforthebiasingcircuitry
Fig. 7 The folded cascode amplifier with the supporting circuitry.
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Ac7vepixels:testsetup
•  8 active pixels
•  7 with injection
enabled
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Fig. 4 A pixel detector circuit under test, to me
Ac7vepixels:injec7on
Fig. 4 has two blocks at the hierarchical level 0.
mirror circuit, used to bias the pmosll4 connected to PBIA
The dark current injection simulating environ
•  InjecHonthroughacurrentmirror
INJECTION WITH RESISTOR
–  nominal1/103reducHonfactor
–  operaHngbelowsaturaHon:1/70-1/94
200 ns
pulser
–  nottoodifferentfromsimulaHon…
Fig. 5 Particle injection s
inj.
padbe written using calculator.
*The skill function can
Vin
*The calculator can be evoked from ADE –> Tools –> Ca
i
M1
imirror
M2
Figure 2.5: Schematic diagram of current gener
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is a current pulse whose pulsewidth is nearly 10 ns. If the
tion of charges in this period of time is nearly 600 e , the
has to generate a 10 nA current. It’s impossible to gene
current. A possible solution is to inject a higher current
ratio of mirrored and injected current. So, M2 width cha
than M1. In our design M2 width channel is 103 times la
mirrored current is 103 times smaller than injected one. S
current is 10 nA, the injected one is nearly 1 µA, which c
by a current generator. So, M2 is a NMOS transistor whos
A.Andreazza-HVR_CCPDand whose length is 400 nm. Instead, M1 length is the9sa
Ac7vepixels:pulseshape
OUTPUT PULSE
InjecHon:
3μA×200ns
Averagedpulse
peak
60mV
Probe
pickup
returntobaseline
~100ns
Singlepulse:
noise~10mVRMS
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Ac7vepixels:linearity
OUTPUT
PULSE
450,0
◼︎Iinj=3 µA (changing pulse length)
▲Iinj=5 µA (changing pulse length)
▲Δt = 100 ns (changing Iinj)
400,0
350,0
OUTPUT PULSE
200,0
180,0
300,0
160,0
140,0
120,0
I=3uA
T=100ns
I=5uA
200,0
V [mV]
V [mV]
250,0
150,0
100,0
80,0
60,0
100,0
40,0
50,0
20,0
0,0
0,0
0
100000
200000
0300000 10000
20000
400000 30000
Q [e]
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40000
500000 50000
60000600000 70000
80000
Q [e]
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Ac7vepixels:comparisonwithsimula7on
Comparison with Simulation (200ns)
140 mV
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263 mV
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Ac7vepixels:comparisonwithsimula7on
Output on KC53AB ACTIVE Pixel
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●
We measured the output noise
of the active
Ac7vepixel:noise
pixels (no input current)
OutBuf Noise ( 6.6 mV rms)
The noise RMS without
nothing connected to the
oscilloscope is ~6 mV
10kHz
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1MHz
100MHz
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10kHz
1MHz
100MHz
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TPM1layout
1.18 mm
pads and general purpose
space
2.5 mm
one
Pixel array
2.8 mm
o specifiche 1
3 mm
4 mm
•  Inspiredfromdemonstratorlayout
(picturebelow)
•  Lateralspacetobetunedtomatch
alignmentwithFE-I4
•  Letoverspaceadbo'omofpixelregion
isonly20μm,maybeincreasedin
mulHpleofthe50μmpixelsize.
tà di
2-8 mA
0.25 mm
available space
out
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Pixelcell
Pixel block-diagram
Genova + Mandi + Milano
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HV-CMOSinATLAS
CPPM
•  Twolargesizedemonstrators:
Monday , February 22, 2016
2
–  AMS180nm(Genève-Karlsruhe),available
–  LFoundry(CPPM-Bonn),submi'ed
MLM3_RUN-1(CPPM) - Fev 2016
,505mm
10mm
10mm
SEAT 1
SEAT 2
5,84mm
Othertechnologiesbeing
tested:
•  XFAB(SOI)
•  TowerJazz
Test Features
• Seat 1 : LF-CPIX ( see details)
• Seat 2 : LF-CPIX with new guards rings strategy
• Seat 3 : test features
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Testbeams
Possible (?) time slots for
hardware test
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André Rummler | ITK Pixel Testbeam Activities | CERN, 15.02.2016
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Summaryandshort-termplans
•  Detectedsignalfrompassivediodes
–  sHlltofullyunderstanddepleHondepthandrate
–  TCAD/Geant4simulaHons(helpwelcome)
–  tryingtoorganizeirradiaHontests
(setupindevelopmentwithPolitecnico)
ATLAS TCAD workshop
CPPM, 11-12 May.
•  FixedKC53ABreceived:
–  allcomponentsareoperaHonal
–  gainlowerthanexpectedandlargedispersion
–  sHlltounderstandmismatchbetweenmeasurementsand
simulaHon
•  Largepixelmatrixtobesubmi'edbymid-April
–  canbematchedtoFE-I4chips
–  possiblyalsotoRD53prototype
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BACKUP
BCD8TechnologySTMicroelectronics
BCD8 Technology
(STMicroelectronics)
BCD = Bipolar + CMOS + DMOS
http://www.st.com/web/en/about st/bcd.html
• D. AmongthecompeHngtechnologiesBCD8hasseveralappealingfeatures:
Riccardi, A. Causio, I. Filippi, A. Paleari, L. Vecchi, A. Pregnolato, P. Galbiati, C. Contiero,
BCD8
from 7V to 70V: a new 0.18 µm technology platform to address the evolution of
–  availabilityofdifferentdevicesintegratedinthesameprocess
applications towards smart power ICs with high logic contents, in Proc. 19th Int. Symp. Power
–  epitaxialprocess:caneasilygrowondifferentsubstrates.
Semiconductor
Devices & ICs, 2007. http://dx.doi.org/10.1109/ISPSD.2007.4294935
–  possibletoreachthickdepleHonlayers:30μmlooksanopHmalcompromisebetween
R. Roggero,
G. Croce, P. Gattari, E. Castellana, A. Molfese, G. Marchesi, L. Atzeni, C. Buran,
signalandmaterialthicknessofthedetector
A. Paleari, G. Ballarin, S. Manzini, F. Alagi, G. Pizzo, BCD8sP: An advanced 0.16 µm
–  long-termavailability:itisoneofthemajorproducHonlineforSTautomoHveproducts.
technology platform with state of the art power devices, in Proc. 25th Int. Symp. Power
Semiconductor Devices & ICs, 2013. http://dx.doi.org/10.1109/ISPSD.2013.6694422
HVR_CCPD-LNSPAC
Catania,17novembre2015
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Noiseperformance
S/N~2for600esignal
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CMP
cmp.imag.fr
•  BCD8nowavailablealso
throughCMP
–  easiertogetnewpeople
started
–  increaseofcostswith
respecttoiniHalinformal
contacts:
•  2600Euro/mm2
ifArea≤5mm2
•  13000Euro
+[(Area-5)*2100Euro]
if5mm2<Area<15mm2
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